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fedd56v161 61n - 0 1 issue date : april 27, 2016 msm56v161 61n 2 - bank524,288 - word16 - bit synchronous dynamic ram 1 / 44 description the msm 56v16161n is a 2 - bank ? 524,288 - word ? 16 - bit synchronous dynamic ram . the device operates at 3.3v. the inputs and outputs are lvttl compatible. features product name msm 56v16161n organization 2 bank x 524,288word x 16 bit address siz e 2,048row x 256column power supply vcc (core) 3.3 v ? 0. 3 v power supply vccq (i/o) 3.3 v ? 0. 3 v interface lv ttl compatible operating frequency max. 1 66 mhz (speed rank 6 ) operating temperature 0 to 70 c function standard sdram command interface / cas late ncy 2, 3 burst length 1, 2, 4, 8, full page burst type sequential, interleave write mode burst, single refresh a uto - refresh, 4,096cycle/64ms ( 0 c ? ta ? 70 c), self - refresh package 50 - pin plastic tsop(ii) (cu frame) (p - tsop (2) 50 - 400 - 0.80 - zk) product family family max. frequency access time (max.) tac2 tac3 msm 56v16161n - 6 166mhz 5.4ns 5.4ns msm 56v16161n - 7 143mhz 5.4ns 5.4ns msm 56v16161n - 75 133mhz 5.4ns 5.4ns msm 56v16161n - 10 100mhz 6ns 6ns
fedd56v161 61n - 0 1 msm56v161 61n 2 / 44 pin configuration (top view) pin name function pin name function clk system clock udqm, ldqm data input / output mask / cs chip select dqi data input / output cke clock enable vcc power supply (3.3v) a0 to a10 address vss ground (0v) a11 bank select address vc c q data output power supply (3.3v) / ras row address strobe vss q data output ground (0v) / cas column address strobe nc no connection / we write enable note : the same power supply voltage must be provided to every vcc pin . the same power supply voltage must be provided to every vcc q pin. the same gnd voltage level must be provided to every vss pin and vss q pin. 50 - pin plastic tsop(ii) 24 19 20 21 22 23 14 15 16 17 18 7 44 37 36 35 34 33 32 31 30 29 28 27 a11 a10 vssq vccq vccq vss nc udqm nc a8 a7 a6 /we /cas /ras /cs a0 a1 a2 ldqm a5 a4 clk cke 1 2 3 4 5 6 8 9 10 11 12 13 50 49 48 47 46 45 43 42 41 40 9 38 dq0 dq1 vcc vc cq vss vccq dq12 dq11 dq10 vssq dq5 vssq dq6 dq7 dq2 dq3 dq4 dq9 dq8 dq13 dq15 dq14 vssq a3 a9 26 25 vcc 39
fedd56v161 61n - 0 1 msm56v161 61n 3 / 44 pin description clk clock (input) fetches all inputs at the h edge. cke clock enable (input) masks system clock to deactiva te the subsequent clk operation. if cke is deactivated, system clock will be masked so that the subsequent clk operation is deactivated. cke should be asserted at least one cycle prior to a new command. / cs chip select (input) disables or enables device o peration by asserting or deactivati ng all inputs except clk, cke and udqm, ldqm . / ras row address strobe (input) functionality depends on the combination with other signals. for detail, see the function truth table. / cas column address strobe (input) fun ctionality depends on the combination with other signals. for detail, see the function truth table. / we write enable (input) functionality depends on the combination with other signals. for detail, see the function truth table. a11 bank address (input) s lects bank to be activated during row address latch time and selects bank for precharge and read/write during column address latch time. a 0 to a 1 0 row & column multiplexed. (input) row address : ra0 C ra10 column address : ca0 C ca 7 dq 0 to dq 15 3 - state data bus (input/output) udqm, ldqm dq mask (input) masks the read data of two clocks later when dqm are set h at the h edge of the clock signal. masks the write data of the same clock when dqm are set h at the h edge of the clock signal. u dqm cont rols dq 7 to dq 15 , ldqm controls dq 0 to dq 7 . vcc , vss power supply (core), ground (core) the same power supply voltage must be provided to every vcc pin. the same gnd voltage l evel must be provided to every vss pin. vccq , vssq power supply (i/o), ground (i/o) the same power supply vol tage must be provided to every vcc q pin. the same gnd voltage level must be provided to every vss q pin. nc no connection
fedd56v161 61n - 0 1 msm56v161 61n 4 / 44 electrical characteristics absolute maximum ratings parameter symbol value unit voltage on input /output pin relative to vss vin, vout C C C C notes: 1. permanent device damage may occur if absolute maximum ratings are exceeded. 2. functional operation should be restricted to recommended operating condition. 3. exposure to higher than recommended voltage f or extended periods of time could affect device reliability. 4. the voltages are referenced to vss. recommended operating conditions (1/2) ta= 0 to 70 ? c parameter symbol min . typ. max . unit note power supply voltage (core) vcc 3.0 3.3 3.6 v 1 power s upply voltage (i/o) vccq 3.0 3.3 3.6 v 1 ground vss, vssq 0 0 0 v notes: 1. the voltages are referenced to vss 2. the power supply voltages should input stable voltage. the power supply voltages should not input oscillated voltage. if voltages recom mended operating conditions (2/2) ta= 0 to 70 ? c parameter symbol min . max. unit note input high voltage vih 2.0 vcc + 0. 3 v 1, 2 input low voltage vil ? notes: 1. the voltages are referenced to vss . 2. the input voltage is vcc + 0.5 v when the pulse width is less than 20 ns (the pulse width is with respect to the point at which vcc is applied). 3. the input voltage is ? 0.5 v when the pulse width is less than 20 ns (the pulse width respect to the point at which vss and vssq are applied).
fedd56v161 61n - 0 1 msm56v161 61n 5 / 44 pin capacitance t a = 25c, vcc vccq 3.3v, f 1mhz parameter symbol min. max. unit input capacitance (clk) cclk ? 4 pf input capacitance ( a0 to a11 , / ras, / cas, / we, / cs, cke, udqm, ldqm ) cin ? 5 pf input/output capacitance (dq 0 to dq 15 ) cout ? 6 . 5 pf dc characteristics (input/output) ? w h en output driver strength=100%, 50%, 25% ta= 0 to 70 c vcc = vcc q = 3.0v~3.6 v parameter symbol condition min. max. unit output high voltage voh ioh = ? ? = 2 ma ? ? ? ? note : the voltages are referenced to vss . ? w h en output driver strength=12.5% ta= 0 to 70 c vcc = vcc q = 3.0v~3.6 v parameter symbol condition min. max. unit output high voltage voh ioh = ? ? = 0.5ma ? ? ? ? note : the voltages are referenced to vss.
fedd56v161 61n - 0 1 msm56v161 61n 6 / 44 dc characteristics (power supply curr ent) ta= 0 to 70 c vcc = vccq = 3.0v~3.6v parameter symbol condition msm 56v16161n unit note - 6 - 7 - 7 5 - 10 bank cke others max. max. max. max. average power supply current (operating) icc1 one bank active cke vih t cc = min. t rc = min. no bu rst 120 100 90 70 ma 1, 2 power supply current (standby) icc2 both banks precharge cke vih t cc = min. 50 40 35 30 ma 3 average power supply current (clock suspension) icc3s both banks active cke vil t cc = min. 3 3 3 3 ma 2 average power supp ly current (active standby) icc3 one bank active cke vih t cc = min. 50 45 40 35 ma 3 power supply current (burst) icc4 both banks active cke vih t cc = min. 160 140 130 100 ma 1, 2 power supply current (auto - refresh) icc5 one bank active ck e vih t cc = min. t rc = min. 160 140 130 100 ma 2 average power supply current (self - refresh) icc6 both banks precharge cke vil t cc = min. 2 2 2 2 ma average power supply current (power down) icc7 both banks precharge cke vil t cc = min. 2 2 2 2 ma notes: 1. measured with outputs open . 2. the a ddress and data can be changed once or left unchanged during one cycle. 3. the a ddress and data can be changed once or left unchanged during two cycles.
fedd56v161 61n - 0 1 msm56v161 61n 7 / 44 ac characteristics (1/2 ) ta= 0 to 70 c vcc = vcc q = 3.0v~3.6v note1,2 parameter symbol msm 56v16161n unit note - 6 - 7 - 75 - 10 min. max. min. max. min. max. min. max. clock cycle time cl=3 t cc3 6 ? ? ? ? ns cl=2 t cc2 10 ? ? ? ? ns access time from clock cl=3 t ac3 ? ? ? ? ns 3,4 cl=2 t ac2 ? ? ? ? ns 3,4 clock high pulse time t ch 2 ? ? ? ? ns 4 clock low pulse time t cl 2 ? ? ? ? ns 4 input setup time t si 2 ? ? ? ? ns input hold time t hi 1 ? ? ? ? ns output low impedance time from clock t olz 2 ? ? ? ? ns output high impedance time from clock t ohz ? ? ? ? ns output hold from clock t oh 2 ? ? ? ? ns 3 random read or write cycle time t rc 60 ? ? ? ? ns ras precharge time t rp 18 ? ? ? ? ns ras pulse width t ras 42 10 5 42 10 5 4 5 10 5 50 10 5 ns /ras to /cas delay time t rcd 18 ? ? ? ? ns write recovery time t wr 2 ? ? ? ? cycle 6 /ras to /ras bank active delay time t rrd 10 ? ? ? ? ns refr esh time t ref ? ? ? ? ms 5 power - down exit setup time t pde t si +1clk ? t si +1clk ? t si +1clk ? tsi+1clk ? ns refresh cycle time t rca 60 ? ? ? ? ns
fedd56v161 61n - 0 1 msm56v161 61n 8 / 44 ac characteristics ( 2 /2) ta= 0 to 70 c vcc = v cc q = 3.0v~3.6v note1,2 parameter symbol msm 56v16161n unit note - 6 - 7 - 75 - 10 /cas to /cas delay time (min.) l ccd 1 1 1 1 cycle clock disable time from cke l cke 1 1 1 1 cycle data output high impedance time from udqm, ldqm l doz 2 2 2 2 cycle dada input mask time from udqm, ldqm l dod 0 0 0 0 cycle data input mask time from write command l dwd 0 0 0 0 cycle data output high impedance time from precharge command l roh cl cl cl cl cycle active command input time from mode register set command input (min.) l mrd 2 2 2 2 cycle write co mmand input time from output l owd 2 2 2 2 cycle note s: 1. ac measurements assume that tt = 1ns,. 2. test condition parameter test condition unit input voltage for ac measurement 2.4 0.4 v transition time for ac measurement tt 1 ns reference level for timing of input signal (tt ? 1ns ) 1.4 v reference level for timing of input signal (tt > 1ns ) vih min. vil max. v reference level for timing of output signal 1.4 v 3. output load. 4. if tt is longer than 1ns, t hen the reference level for timing of input signals is vih and vil . 5. it is necessary to operate auto - refresh 4096 cycles within tref. 6. if tcc is longer than 20ns, the spec of twr (min.) is 20ns (1 cycle ). o ut pu t z=50 ? 30pf (external load) 1.4v 50 ?
fedd56v161 61n - 0 1 msm56v161 61n 9 / 44 power on and initialize power on sequence 1. app ly power and attempt to maintain cke= h and other pins are nop condition at the input. 2. maintain stable power, stable clock and nop input condition for a minimum of 200 ? s . 3. issue precharge commands for all banks of the devices. 4 . issue mode register set command to initialize the mode register. 5 . issue extended mode register set command to initialize the extended mode register. 6. issue 2 or more auto - refresh commands. note 1: (4), (5) or (6): in no special order. 2. (5) can be omitted. when it is omitted, it becomes default settings. 3. carry out an initialization sequence after each input terminal reaches a regulation voltage when other input terminals were the undefined setup input (high - z) at the cke= "h" time. and, the undefined setup input per iod of the cke= "h" time can't hold data. it becomes more effective than writing data after the initialization sequence. mode register set command (mrs) the mode register stores the data for controlling the various operating modes. it programs the / cas latency, burst type, burst length and write mode. the default value of the mode register is not defined, therefore the mode register must be written after power up to operate the sdram. the mode register is written by mode register set command mrs. the sta te of address pins a0 to a 1 0 in the same cycle as mrs is the data written in the mode register. refer to the table for specific codes for various / cas latencies, burst type, burst length and write mode. extended mode register set command (emrs) th e extended mode register stores the data for controlling output driver strength. the default value of the extended mode register is defined. therefore the mode register must be written after power up to operate the sdram. the extended mode register is writ ten by extended mode register set command em rs. the state of address pins a 0 to a 1 0 in the same cycle as emrs is the data written in the extended mode register. refer to the table for extended mode register set address keys . mrs clk n - 1 n cke h x / cs x (idle) l / ras l / cas l / we l a11 x 0 a0 to a 1 0 v v v: the value of mode register set emrs clk n - 1 n cke h x /cs x (idle) l / ras l / cas l / we l a11 x 1 a0 to a10 v v v: the value of extended mode register set
fedd56v161 61n - 0 1 msm56v161 61n 10 / 44 mode register field table to program mode write burst mode / cas latency burst type burst length a9 wm a6 a5 a4 cl a3 bt a2 a1 a0 bt = 0 bt = 1 0 burst 0 0 0 reserved 0 sequential 0 0 0 1 1 1 single 0 0 1 reserved 1 interleave 0 0 1 2 2 0 1 0 2 0 1 0 4 4 0 1 1 3 0 1 1 8 8 1 0 0 reserved 1 0 0 reserved reserved 1 0 1 reserved 1 0 1 reserved reserved 1 1 0 reserved 1 1 0 reserved reserved 1 1 1 reserved 1 1 1 full page reserved notes: 1. 1. objects are all family products. 2. a11 should stay 0 during mode set cycle. 3 . a7, a8 and a10 should stay 0 during mode set cycle. 4 . dont set address keys of reserved . extended mode register set address keys output driver strength a6 a5 ds 0 0 full (default) 0 1 1/2 1 0 1/8 1 1 1/4 notes: 1. a11 should s tay 1 during mode set cycle. 2. a0 to a4, a7 to a10 should stay 0 during mode set cycle. 3. if don t set emrs, ds is set to d efault (full).
fedd56v161 61n - 0 1 msm56v161 61n 11 / 44 output driver characteristics (1/2) ta 0c~+70c , vcc,vccq 3 .0 v ~3.6v output dri ver strength= full (default) output driver strength=1/ 2 min. max. typ. min. max. typ. min. max. typ. mi n. max. typ.
fedd56v161 61n - 0 1 msm56v161 61n 12 / 44 output driver characteristics (2/2) ta 0c ~+70 c, vcc,vccq 3 .0 v ~3.6v output driver strength=1/4 output driver strength=1/8 min. max. typ. min. max. typ. max. min. typ. max. min. typ.
fedd56v161 61n - 0 1 msm56v161 61n 13 / 44 burst mode burst operation is the operation to contin uously increase a column address inputted during read or write command. the upper bits select a column address block, access order in column address block start address (lower bit) burst type bt=sequential bt=interleave burst length bl=2 a0 0 0, 1 0, 1 1 1, 0 1, 0 bl=4 a1 a0 0 0 0, 1, 2, 3 0, 1, 2, 3 0 1 1, 2, 3, 0 1, 0, 3, 2 1 0 2, 3, 0, 1 2, 3, 0, 1 1 1 3, 0, 1, 2 3, 2, 1, 0 bl=8 a2 a1 a0 0 0 0 0, 1, 2, 3, 4, 5, 6, 7 0, 1, 2, 3, 4, 5, 6, 7 0 0 1 1, 2, 3, 4, 5, 6, 7, 0 1, 0, 3, 2, 5, 4, 7, 6 0 1 0 2, 3, 4, 5, 6, 7, 0, 1 2, 3, 0, 1, 6, 7, 4, 5 0 1 1 3, 4, 5, 6, 7, 0, 1, 2 3, 2, 1, 0, 7, 6, 5, 4 1 0 0 4, 5, 6, 7, 0, 1, 2, 3 4, 5, 6, 7, 0, 1, 2, 3 1 0 1 5, 6, 7, 0, 1, 2, 3, 4 5, 4, 7, 6, 1, 0, 3, 2 1 1 0 6, 7, 0, 1, 2, 3, 4, 5 6, 7, 4, 5, 2, 3, 0, 1 1 1 1 7, 0, 1, 2, 3, 4, 5, 6 7, 6, 5, 4, 3, 2, 1, 0 bl=full page (256) a0 to a7 0 0, 1 255 non support yn yn, yn+1 255, 0 yn - 1
fedd56v161 61n - 0 1 msm56v161 61n 14 / 44 read / write operation bank this sdram is organized as four independent banks of 524,288 words x 16 bits memory arrays. the a11 input is latched at the time of assertion of / ras and / cas to select the bank to be used for operation. the bank address a11 is latched at bank active, read, write, mode register s et and precharge operations. activate the bank activate command is used to select a random row in an idle bank. by asserting low on / ras and / cs with desired row and bank address, a row access is initiated. the read or write operation can occur afte r a time delay of trcd(min) from the time of bank activation. precharge the precharge operation is performed on an active bank by precharge command (pre) with valid a11 of the bank to be precharged. the precharge command can be asserted anyti me after t ras (min) is satisfied from the bank active command in the desired bank. all bank can precharged at the same time by using precharge all command (pall). asserting low on / cs , / ras and / we with high on a10 after all banks have satisfied t ras (min) r equirement, performs precharge on al banks. at the end of t rp after performing precharge to all banks, all banks are in idle state. bank address a11 bank 0 a 1 b act clk n - 1 n cke h x / cs x (idle) l / ras l / cas h / we h a11 x ba a0 to a 1 0 x ra ba: bank address ra: row address (page) pall clk n - 1 n cke h x / cs x (p age open) l / ras l / cas h / we l a11 x x a10 x 1 a0 to a 9 x x pre clk n - 1 n cke h x / cs x (page open) l / ras l / cas h / we l a11 x ba a10 x 0 a0 to a 9 x x ba: bank address
fedd56v161 61n - 0 1 msm56v161 61n 15 / 44 write / write with auto - precharge the write command is used to write data into the sdram on consecutive clock cycles in adjacent address depending on burst length and burst sequence. by asserting low on / cs , / cas and / we with valid column address, a write burst is initiated. the data inputs are provided for the initial address in the same clock cycle as the burst write com mand. the input buffer is deselected at the end of the burst length, even through the internal writing can be completed yet. the writing can be completed by issuing a burst read and dqm for blocking data inputs or burst write in the same or another active bank. the burst stop command is valid at every burst length. write cycle wrta clk n - 1 n cke h x / c s x (page ope n) l / ras h / cas l / we l a11 x ba a10 x 1 a9, a8 x x a0 to a7 x ca dq x d - in ba: bank address ca: column address d - in: data inputs wrt clk n - 1 n cke h x / cs x (page open) l / ras h / cas l / we l a11 x ba a10 x 0 a9, a8 x x a0 to a7 x ca dq x d - in ba: bank address ca: column address d - in: data inputs wrt wrt wrta pre pre act a ct act act act d0 d0 d1 d2 d3 tras trp trp tras twr trp twr auto precharge start page open d0 d1 d2 d3 clk cl=2 or 3, bl=1 or wm=single command dq cl=2 or 3, bl=4, wm=burst command dq cl=2 or 3, bl=4, wm=burst command dq valid burs t data in valid single data in trcd trcd
fedd56v161 61n - 0 1 msm56v161 61n 16 / 44 read / read with auto - precharge the read command is used to access burst of data on consecutive clock cycles from an active row in an active bank. the read command is issued b y asserting low on / cs and / cas with / we being high on the positive edge of the clock. the bank must be active for at least t rcd (min) before the read command is issued. the first output appears in / cas latency number of clock cycles after the issue of read command. the burst length, burst sequence and latency from the read command are determined by the mode register that is already programmed. read cycle rda clk n - 1 n cke h x / cs x (page open ) l / ras h / cas l / we h a11 x ba a10 x 1 a9, a8 x x a0 to a7 x ca dq x x ba: bank address ca: column address rd clk n - 1 n cke h x / cs x (page open ) l / ras h / cas l / we h a11 x ba a10 x 0 a9, a8 x x a0 to a7 x ca dq x x ba: bank address ca: column address rd rd pre pre act act act act q0 tras trp trp tras trp auto precharge start page open q1 q2 q3 q0 q1 q2 q3 rda q0 q1 q2 q3 trp auto precharge start rda q0 q1 q2 q3 clk cl=2, bl=4 command dq cl=3, bl=4 command dq cl=2, bl=4 command dq cl=3, bl=4 command dq page open /cas latency (cl) = 2 /cas latency (cl) = 3 valid burst data out valid bur st data out trcd trcd act act
fedd56v161 61n - 0 1 msm56v161 61n 17 / 44 write / write interrupt when a new write command is issued to same bank during write cycle or another active bank, current burst write is terminated and new burst write start. when a new write command is issued to another bank during a write with auto - precharge cycle, current burst is terminated and a new write command start. then , current bank is precharged after specified time. don t issue a new write command to same bank during write with auto - precharge cycle. write / write interrupt cycle da0 db0 db1 dc0 dc1 dc2 dc3 tccd tccd wrta wrtb wrtc wrta da0 wrta db0 da1 db1 db2 db3 act a act b a b twr + 1clk trp auto precharge burst write burst int errupt , write recovery row active burst write auto precharge write recovery row active twr trp tccd trrd clk cl=2 or 3, bl=4, wm=burst command dq cl=2 or 3, bl=4, wm=burst command dq cl=2 or 3, bl=4, wm=burst command bank address ban k a internal state bank b internal state dq wrta wrtab da0 db0 db1 db2 db3 tccd twr ac t trp auto precharge start row active da1
fedd56v161 61n - 0 1 msm56v161 61n 18 / 44 read / read interrupt when a new read command is issued to same bank during read cycle or another active bank, current burst read is terminated after the cycle same as / cas latency and new bu rst read start. when a new read command is issued to another bank during a read with auto - precharge cycle, current burst is terminated after the cycle same as / cas latency and a new read command start. then , current bank is precharged after specified time. don t issue a new read command to same bank during read with auto - precharge cycle. read / read interrupt cycle rda qa0 qb0 qb1 qc0 qa0 qb1 qb2 rdb qc1 rdc qc2 qc3 tccd high - z rda qb0 tccd tccd qb3 act trp rdab high - z auto precharge start clk cl=2, bl=4 command dq cl=3, bl=4 command dq cl=2, bl=4 command bank address bank a internal state bank b internal state dq rda rda qa0 qa1 a b qb0 qb1 qb2 qb3 auto precharge burst read burst interrupt row active burst read auto precharge row active act a act b ro w active tccd trrd trp + 1clk t rp qa1
fedd56v161 61n - 0 1 msm56v161 61n 19 / 44 write / read interrupt when a new read command i s issued to same bank during write cycle or another active bank, current burst write is terminated and new burst read start. when a new read command is issued to another bank during a write with auto - precharge cycle, current burst is terminated and a new r ead command start. then , current bank is precharged after specified time. don t issue a new read command to same bank during write with auto - precharge cycle. dq must be hi - z till 1 or more clock from first read data. write / read interrupt cycle qb1 qb2 rdb qb3 tccd high - z wrta da0 wrta tccd da0 da1 qb1 qb2 qb3 high - z auto precharge start trp rdab act invalid data input invalid data input qb0 qb0 wrta rda act a b tccd clk cl=3, bl=4, wm=burst command dq cl=2, bl=4, wm=burst command dq cl=2, bl=4, w m=burst command bank address bank a internal state bank b internal state dq burst write twr + 1clk burst interrupt , write recovery auto precharge trp act row active row active auto precharge da0 da1 trp a b invalid data input qb1 q b2 qb3 high - z qb0 burst read trrd row active
fedd56v161 61n - 0 1 msm56v161 61n 20 / 44 read / write interrupt when a new write command is issued to same bank during read cycle or another active bank, current burst read is terminated and new burst write start. when a new write command is issued to another bank during a read with auto - precharge cycle, current burst is terminated and a new write command start. then , current bank is precharged after specified time. don t issue a new write command to sa me bank during read with auto - precharge cycle. dq must be hi - z till 1 or more clock from new write command. therefore, dqm must be high till 3 clocks from new write command. read / write interrupt cycle qa0 db0 rda db1 wrtb db2 db3 high - z qa0 db0 rda db1 wrta db2 db3 high - z towd towd clk cl=3, bl=4, wm=burst command dqm dq cl=2, bl=4, wm=b urst command bank address bank a internal state bank b internal state dqm dq a b burst read auto precharge row active burst interrupt act a row active burst write auto precharge write recovery twr trp + 1clk
fedd56v161 61n - 0 1 msm56v161 61n 21 / 44 burst stop when a burst stop command is issued during read cycle, current burst read is terminated. the dq is to hi - z after the cycle same as / cas latency and page keep open. when a burst stop command is issued during write cycle, current burst write is terminated. the input data is ignored after burst stop command. don t issue burst stop command during read with auto - precharge cycle or write with auto - precharge cycle. read / burst stop cycle write / burst s top cycle bst clk n - 1 n cke h x / cs x (burst) l / ras h / cas h / we l a11 x x a0 to a10 x x rd q0 q1 q2 q0 q2 bst high - z rd q1 high - z clk cl=2, bl=4~full command dq cl=3, bl=4~full command dq bst wrt d0 d1 d2 bst high - z invalid data input clk cl=2 or 3, bl=4~full, wm=burst command dq
fedd56v161 61n - 0 1 msm56v161 61n 22 / 44 precharge break when a precharge command is issued to the same bank during read cycle or precharge all command is issued, current burst read is terminated and dq is to hi - z after the cycle same as / cas latency. the objected bank is precharged. when a precharge command is issued to the same bank during write cycle or precharge all command is issued, current burst write is terminated and the objected bank is precharged. the input data after precharge command is ignored. read / precharge break cycle write / precharge break cycle pr e q0 q1 rd q2 clk cl=2, bl=4~full command dq cl=3 bl=4~full command dq tras trp high - z q0 q2 rd q1 high - z pre act trcd act act tras trp act trcd pre d0 d1 wrt tras trp act trcd act invalid data input clk cl=2, bl=4~full command dqm dq cl=3, bl=4~full command dqm dq act pre d0 d1 wrt d2 tras trp trcd act twr twr
fedd56v161 61n - 0 1 msm56v161 61n 23 / 44 dqm function dqm masks input / output data at every byte. udqm controls dq 8 to dq 15 and l dqm controls dq 0 to dq 7 . during read cycle, dqm mask output data after 2 clocks. d uring write cycle, dqm mask input data at same clock. read / dqm function write / dqm function qu0 rd qu1 high - z qu4 qu6 qu7 ql0 ql3 ql4 ql6 ql7 high - z high - z high - z high - z high - z clk cl=3, bl=8 command udqm dq8 to dq15 ldqm dq0 to dq7 du0 wrt du1 du4 du6 du7 dl0 dl3 dl4 dl6 dl7 invalid data input clk cl=2 or 3, bl=8 command udqm dq8 to dq15 ldqm dq0 to dq7
fedd56v161 61n - 0 1 msm56v161 61n 24 / 44 clock suspend the read / write operation can be stopped by cke temporaril y. when cke is set low, the next clock is ignored. when cke is set low during read cycle, the burst read is stopped temporarily and the current output data is kept. when cke is set high, burst read is resumed. when cke is set low during write cycle, the bu rst write is stopped temporarily. when cke is set high, burst write is resumed. read / clock suspend write / clock suspend clk cl=2 or 3, bl=8 cke command dq d0 wrt d1 d2 d4 d5 invalid data input d3 d6 suspend c l = 2, b l = 8 c k e c o m m suspend q0 rd q2 q4 q3 q1 clk cl=2, bl=8 cke command dq q5 suspend suspend valid data output
fedd56v161 61n - 0 1 msm56v161 61n 25 / 44 refresh the data of memory cells are maintained by refresh oper ation. the refresh operation is to activate all row addresses within a refresh time. the method that row addresses are activated by activate and precharge command is called ras only refresh cycle. this method needs to input row address with activate comman d. but, auto - refresh and self refresh don t need to input address. because, row addresses are generated in sdram automatically. auto refresh all memory area is refreshed by 4,096 times refresh command ref. the refresh command ref can be entered only wh en all the banks are in an idle state. sdram is in idle state after refresh cycle time trca . auto - refresh cycle intensive refresh 4,096 times refresh command can be entered every refresh time t ref . dispersed refres h refresh command can be entered every 15.6 ? s ( tref 64 ms / 4,096 cycles). ref clk n - 1 n cke h h / cs x (idle ) l / ras l / cas l / we h a11 x x a0 to a10 x x clk command ref pall ref act trp trca trca ref x 4,096 clk state read or write auto refresh read or write a uto refresh ref x 4,096 tref=64ms tref=64ms clk state r/w ref 4,096 times tref=64ms r/w ref r/w ref r/w ref 15.6s ref 15.6s 15.6s
fedd56v161 61n - 0 1 msm56v161 61n 26 / 44 self refresh when read or write is not operated in the long period, self refresh can reduce power c onsumption for refresh operation. r efresh operation is controlled automatically by refresh timer and row address counter during self refresh mode. all signals except cke are ignored and data bus dq is set hi - z during self refresh mode. when cke is set to h igh level, self refresh mode is finished. then, clk must be operated before 1 clock or more. and, maintain nop condition within a period of trca (min.) after cke is set to be high level. self refresh cycle notes : 1. when intensive refresh is used, 4,096 times refresh must be issued before and after the self refresh. clk cke command ref trca self refresh trca sref ref sref clk n - 1 n cke h l / cs x (idle) l / ras l / cas l / we h a11 x x a0 to a10 x x
fedd56v161 61n - 0 1 msm56v161 61n 27 / 44 power down sdram can be set to low power consumption condition with cke function. cke is reflected at 1 clock later regardless / cas laten cy. when cke is set to low level, sdram go into power down mode. all signals except cke are ignored and dq is set to high impedance in this state. when cke is set to high level, sdram exit power down mode. then, clock must be resumed before 1 or more clock s. power down signal condition in power down mode signal input to sdram output from sdram clk don t care ? cke l level ? / cs, / ras, / cas, / we don t care ? a0 to a10, a11 don t care ? dq 0 to dq 15 don t care high - z udqm,l dqm don t care ? vcc,vccq,vss,vssq power supply ? notes : 1. don t care means high or low level input. active power do wn mode rd write cycle q0 q1 d2 d3 d1 new command high - z q2 q3 q1 auto precharge start page open stand - by power down mode high - z ref new command precharge stand - by / idle clk cl=2, bl=4, case 1 cke command dq cl=2, bl=4, case 2 cke command dq
fedd56v161 61n - 0 1 msm56v161 61n 28 / 44 function truth table function truth table (table 1) (1/3) current state * 1 / cs / ras / cas / we addr command action idle h x x x x nop nop l h h x x nop/bst nop l h l h ba, ca, a10 rd/rda illegal *2 l h l l ba, ca, a10 wrt/wrta illegal *2 l l h h ba, ra act row active l l h l ba, a10 pre/pall nop *3 l l l h x ref auto - refresh or self - refresh *4 l l l l v, a11 =0 mrs mode register set * 4 l l l l v, a 1 1= 1 emrs extended mode register set *4 row active h x x x x nop nop l h h x x nop/bst nop l h l h ba, ca, a10 rd/rda read / read auto precharge *5 l h l l ba, ca, a10 wrt/wrta write / write auto precharge *5 l l h h ba, ra act ill egal *6 l l h l ba, a10 pre/pall precharge l l l h x ref illegal l l l l x mrs/emrs illegal read h x x x x nop continue row active after burst ends l h h h x nop continue row active after burst ends l h h l x bst term burst -- > row active l h l h ba, ca, a10 rd/rda term burst, start new burst read l h l l ba, ca, a10 wrt/wrta term burst, start new burst write l l h h ba, ra act illegal *6 l l h l ba, a10 pre/pall term burst, execute row precharge l l l h x ref illegal l l l l x mrs/em rs illegal write h x x x x nop continue row active after burst ends l h h h x nop continue row active after burst ends l h h l x bst term burst -- > row active l h l h ba, ca, a10 rd/rda term burst, start new burst read l h l l ba, ca, a10 wrt/wrta term burst, start new burst write l l h h ba, ra act illegal *6 l l h l ba, a10 pre/pall term burst, execute row precharge l l l h x ref illegal l l l l x mrs/emrs illegal
fedd56v161 61n - 0 1 msm56v161 61n 29 / 44 function truth table (table 1) (2/3) current state *1 / cs / ras / cas / we addr command action read with auto precharg e h x x x x nop continue burst to end and enter row precharge l h h h x nop continue burst to end and enter row precharge l h h l x bst illegal l h l h ba, ca, a10 rd/rda illegal *7 l h l l ba, ca, a10 wr t/wrta illegal *7 l l h h ba, ra act illegal *6 l l h l ba, a10 pre/pall illegal *8 l l l h x ref illegal l l l l x mrs/emrs illegal write with auto precharge h x x x x nop continue burst to end and enter row precharge l h h h x nop continue bur st to end and enter row precharge l h h l x bst illegal l h l h ba, ca, a10 rd/rda illegal *7 l h l l ba, ca, a10 wrt/wrta illegal *7 l l h h ba, ra act illegal *6 l l h l ba, a10 pre/pall illegal *8 l l l h x ref illegal l l l l x mrs/emrs i llegal precharge h x x x x nop idle after t rp l h h h x nop idle after t rp l h h l x bst illegal l h l h ba, ca, a10 rd/rda illegal *2 l h l l ba, ca, a10 wrt/wrta illegal *2 l l h h ba, ra act illegal *6 l l h l ba, a10 pre/pall illegal *3 l l l h x ref illegal l l l l x mrs/emrs illegal write recovery *9 h x x x x nop row active after t wr l h h h x nop row active after t wr l h h l x bst illegal l h l h ba, ca, a10 rd/rda illegal *2 l h l l ba, ca, a10 wrt/wrta illegal *2 l l h h ba, ra act illegal *6 l l h l ba, a10 pre/pall illegal *8 l l l h x ref illegal l l l l x mrs/emrs illegal
fedd56v161 61n - 0 1 msm56v161 61n 30 / 44 function truth table (table 1) (3/3) current state *1 / cs / ras / cas / we addr command action write recovery in auto precharge *9 h x x x x nop enter row precharge after t wr l h h h x nop enter row precharge after t wr l h h l x bst illegal l h l h ba, ca, a10 rd/rda illegal *7 l h l l ba, ca, a10 wrt/wrta illegal *7 l l h h ba, ra act illegal *6 l l h l ba, a10 pre/pall illegal *8 l l l h x ref illegal l l l l x mrs/emrs illegal auto refresh h x x x x nop idle after t rca l h h h x nop idle after t rca l h h l x bst illegal l h l h ba, ca, a10 rd/rda illegal l h l l ba, ca, a10 wrt/wrta illegal l l h h ba, ra act illeg al l l h l ba, a10 pre/pall illegal l l l h x ref illegal l l l l x mrs/emrs illegal mode register access h x x x x nop idle after tmrd l h h h x nop idle after tmrd l h h l x bst illegal l h l h ba, ca, a10 rd/rda illegal l h l l ba, ca, a1 0 wrt/wrta illegal l l h h ba, ra act illegal l l h l ba, a10 pre/pall illegal l l l h x ref illegal l l l l x mrs/emrs illegal abbreviations addr = address ra = row address ba = bank address ca = column address nop = no operation command v = val ue of mode register set ? notes : 1. all inputs are enabled when cke is set high for at least 1 cycle prior to the inputs. 2. rd/rda or wrt/wrta command to same bank is forbidden . but rd/rda or wrt/wrta command to activated page in another bank is valid after trcd(min.). 3. pre command to another activated bank is valid. pall command is valid to only activated bank. 4. illegal if any bank is not idle. 5. rd/rda or wrt/wrta command to activated bank is valid after trcd (min.) from act command. 6. activate command to the same bank is forbidden . but activate command to another bank in idle state is valid. 7. rd/rda or wrt/wrta command to same bank is forbidden . but rd/rda or wrt/wrta command to activated page in another bank is valid. 8. pre to same bank is forbidden . pre to ano ther bank must be issued after tras (min.). pall command is forbidden . 9. write recovery states means a period from last data to the time that twr (min.) passed.
fedd56v161 61n - 0 1 msm56v161 61n 31 / 44 function truth table for cke (table 2) current state n - 1 cke n - 1 cke n / cs n / ras n / cas n / we n a ddr n action all banks idle (abi) h h x x x x x refer to table 1 h l h x x x x enter power down h l l h h h x enter power down h l l h h l x illegal h l l h l x x illegal h l l l h h ba, ra enter active power down after activate h l l l h l x illegal h l l l l h x enter self refresh *2 h l l l l l ba, v enter power down after mrs l x x x x x x invalid self refresh h x x x x x x invalid l h h x x x x exit self refresh -- > abi *3 l h l h h h x exit self refresh -- > abi *3 l h l h h l x illegal l h l h l x x illegal l h l l x x x illegal l l x x x x x nop (maintain self refresh) power down h x x x x x x invalid l h x x x x x exit power down -- > abi *4 l l x x x x x nop (continue power down) active power down h x x x x x x i nvalid l h x x x x x exit active power down -- > row active *4 l l x x x x x nop (continue active power down) row active h h x x x x x refer to table 1 h l h x x x x enter active power down h l l h h h x enter active power down h l l h h l x ille gal h l l h l x x clock suspension (refer to table 1) h l l l h x x clock suspension (refer to table 1) h l l l l x x illegal l x x x x x x invalid any state other than listed above h h x x x x x refer to table 1 h l x x x x x begin clock suspen d next cycle l h x x x x x enable clock of next cycle l l x x x x x continue clock suspension abbreviations addr = address ra = row address ba = bank address nop = no operation command v = value of mode register set abi = all banks idle *notes : 1. deep power down can be entered only when all the banks are in an idle state. 2. self refresh can be entered only when all the banks are in an idle state. 3. trca must be set after exit self refresh. 4. new command is enabled in the next clock.
fedd56v161 61n - 0 1 msm56v161 61n 32 / 44 simpl ified state diagram power on writea reada write read active idle reada suspend read suspend writea suspend write suspend precharge auto refresh self refresh active power down power down mode register set cke ? cke ? c ke ? cke ? cke ? cke ? cke ? cke ? write read cke ? cke ? burst stop read write burst stop read write precharge read with auto precharge write ap write ap read ap read ap write with auto precharge precharge precharge cke ? cke ? ac tive refresh self refresh exit mrs precharge command / input signal auto sequence extended mode register set emrs
fedd56v161 61n - 0 1 msm56v161 61n 33 / 44 timing chart synchronous characteristics note : the object of input are cke, a0 to a 11 / cs, / ras, / cas, / we, u dqm to l dqm and dq 0 to dq 15 (input) . power on sequence notes : 1. it is advisa ble that u dqm and l dqm are set to high for set dq to high impedance during power on sequence. t t > 1ns t t 1ns high - z t cl t ch t cc2/3 t si t hi t si t hi t ohz t oh t oh high - z t ac2/3 t ac2/3 1.4v input * clk dq output high - z t cl t ch t cc2/3 t si t hi t si t hi t ohz2/3 t oh t oh t ac2/3 t ac2/3 valid high valid low valid high valid low valid high valid low high - z valid high valid low v ih v il v ih v il v oh v ol t ransition time t t ? 1ns t ransition time t t ? 1ns 1.4v 1.4v t olz t olz vcc, vccq clk command (/ cs, / ras, / cas, / we ) address udqm,ldqm dq0 to dq15 nop pall nop ? 200s max. min. 0v stable clock input initialize high - z (nop) don't care don't care *1
fedd56v161 61n - 0 1 msm56v161 61n 34 / 44 initialization notes : 1 . v = value of mode register, rx = row address, bx = bank address = nop command or high or low 2. it is advisa ble that u dqm to l dqm are set to be high level for setting dq to high impedance during power on sequence. mode register set cycle notes : 1. v = value of mode register, rx = row address, bx = bank address = nop command or high or low clk cke command (/ cs, / ras, / cas, / we ) address a10 a11 udqm,ldqm dq0 to 15 ra v ba t rp pall mrs emrs ref ref act high v ra ? 200s t mrd t mrd t rca t rca high - z don't care * 2 clk cke command (/ cs, / ras, / cas, / we ) address a10 a11 udqm,ldqm dq0 to 15 ra t rp mrs emrs act v t mrd t mrd t rca h igh - z pre ref sref v ra t ras ba ba t rc t si
fedd56v161 61n - 0 1 msm56v161 61n 35 / 44 burst write cycle (bl=4, wm=burst) notes : 1. rx = row address, cx = column address, bx = bank address = nop command or high or low level, cke = high level burst read cycle (bl=4) notes : 1. rx = row address, cx = column address, bx = bank address = nop command or high or low level, cke = high level clk command (/ cs, / ras, / cas, / we ) address a10 a11 udqm, ldqm (cl=2) dq 0 to 15 (cl=2) udqm, ldqm (cl=3) dq0 to 15 (cl=3) qa0 qa2 qa3 qa2 qa3 qb0 qb0 rd rd ca cb pre bb rb ba bb ba bb t ras t rp t rcd t ras t rc t ac2 t oh act rb ra ba act ra t rcd qa0 t ac2 t oh clk command (/ cs, / ras, / cas, / we ) address a10 a11 udqm, ldqm (cl=2, 3) dq0 to 15 (cl=2, 3) t olz t ohz t olz t ohz t ac3 t oh t olz t ohz t ac3 t oh t olz t ohz qa1 qa1 pre da0 da2 db0 act ra ra ba wrt act wrt ca rb cb pre bb pre rb ba bb ba bb t rc t ras t rp t ras t rcd t rcd t si t hi t si t hi t si t hi t si t hi t si t hi t si t hi t si t hi t si t hi da1 t wr t wr
fedd56v161 61n - 0 1 msm56v161 61n 36 / 44 bank interleave ? notes : 1. rxx = row address, cxx = column address, x = bank, x = addres s = nop command or high or low level, cke = high level bank interleave ? notes : 1. rxx = row address, cxx = column address, x = bank, x = address = nop command or high or low level, cke = high level clk command (/ cs, / ras, / cas, / we ) address a10 a11 udqm, ldqm dq0 to 15 clk command (/ cs, / ras, / cas, / we ) address a10 a11 udqm, ldqm dq0 to 15 qaa0 qaa1 qaa2 qaa3 act raa raa a rda act caa rab cab a rab a a b b t rc (bank - a) t ras (bank - a) t rp (bank - a) t rcd t rcd cba act b rba rba rda qba0 qba1 qba2 qba3 rda act rda rbb cbb rbb b qab0 qab1 qab2 t rcd t rcd t ras (bank - b) t rp (bank - b) t rc (bank - b) t ac2 t oh t olz t ohz t ac2 t oh daa0 daa2 act raa raa a wrta act caa rab cab a rab a a b b t rc (bank - a) t ras (bank - a) t rp (bank - a) t rcd t rcd t si t hi t si t hi cba act b rba rba wrta dba0 dba2 dba3 wrta a ct wrta rbb cbb rbb b dab0 dab2 dbb0 t rcd t rcd t ras (bank - b) t rp (bank - b) t rc (bank - b) t wr t wr t si t hi t si t hi daa1 daa3 dba1 dab1 dab3
fedd56v161 61n - 0 1 msm56v161 61n 37 / 44 burst read ? notes : 1.rxx = row address, cxx = column address, x = bank, x = address = nop command or high or low level, cke = high level random column ? notes : 1. rxx = row address, cxx = column address, x = bank, x = address = nop command or high or low level, cke = high level, = invalid data input clk command (/ cs, / ras, / cas, / we ) address a10 a11 udqm, ldqm dq0 to 15 qaa0 qab0 caa a a ct cac b a t rrd cab qac0 qad0 dba0 t owd t ac3 t olz t oh wrt daf0 qbc0 t ccd rd rd rd cad rba a a a b rd pre rd wrt act rd wrt wrt rd rd rab cba cae cbb caf cbc cag cbd cah rba a b b a a b a a dbb0 dae0 t ac3 t olz t ccd t ccd t ccd t ccd t ccd t ccd t ccd t ccd t ccd t rp (bank - a) t rcd (bank - b) (bank - a=active) t rcd (bank - a) t oh rab t si t hi t ohz clk command (/ cs, / ras, / cas, / we ) address a10 a11 udqm,ldqm dq0 to 15 qaa0 qaa1 act raa raa a rd act cab a a b t rcd t rcd cba b rba qaa2 qaa3 dba cbb b t owd t ac2 t olz t oh wrt wrt rd dbb qab0 t ac2 t olz t oh rba t ccd t si t hi t si t hi t ohz2 t ccd caa
fedd56v161 61n - 0 1 msm56v161 61n 38 / 44 burst stop ? notes : 1. cx = column address, bx = bank address = nop command or high or low level, cke = high level, = invalid data input precharge break ? notes : 1. rxx = row address, cxx = column address, x = bank, x = address = nop command or hig h or low level, cke = high level, = invalid data input clk comman d (/ cs, / ras, / cas, / we ) address a10 a11 udqm, ldqm (cl=2) dq0 to 15 (cl=2) udqm, ldqm (cl=3) dq0 to 15 (cl=3) clk command (/ cs, / ras, / cas, / we ) address a10 a11 udqm, ldqm (cl=2) dq0 to 15 (cl=2) udqm, ldqm (cl=3) dq0 to 15 (cl=3) qa0 ca ba t wr db0 t owd t ac2 t olz t oh rd bst cb ba wrt bst dbn - 1 dbn pre ba t si t hi t ohz qa0 t wr qan - 2 db0 t owd t ac3 t olz t oh dbn - 1 t si t hi t ohz qa1 qan - 1 db1 qan qan - 1 db1 qan ca ba rd pre cb ba wrt pre ba qa0 t wr db0 t owd t ac2 t olz t oh t si t hi t ohz qa0 t wr db0 t owd t ac3 t olz t si act ba rb rb ba t rp t ras t rcd t oh qan - 1 qan qan - 2 dbn - 1 dbn - 1 t ohz qan - 1 qan t hi db1 db1 qa1 dbn
fedd56v161 61n - 0 1 msm56v161 61n 39 / 44 byte read / byte write cycle (cl=2, bl=8 , wm=burst ) notes : 1. cx = column address, bx = bank address = nop command or high or low level, cke = high level, = invalid data input clock suspend ? notes : 1. cx = column address, bx = bank address = nop command or high or low level, cke = high level, = invalid data input clk cke command (/ cs, / ras, / cas, / we ) address a10 a 11 udqm, ldqm dq0 to 15 rd wrt ca cb ba ba qa0 db1 db2 qa1 db3 t si t hi t si t hi t ac3 t olz t oh t si t hi t ohz t owd clk command ( /cs, /ras, /cas, /we ) address a10 a11 udqm dq 8 to 15 ldqm dq 0 to 7 rd wrt ca cb ba ba qa0 db0 db1 qa1 qa4 qa5 db4 db5 qa0 db0 db2 qa2 qa4 qa5 db4 db5 t ohz t olz t si t hi t si t hi qa3 qa2 db0
fedd56v161 61n - 0 1 msm56v161 61n 40 / 44 auto refresh cycle notes : 1. rx = row address, bx = bank address = nop command or high or low level, cke = high level, = invalid data input self refresh cycle notes : 1. rx = row address, bx = bank address = high or low level clk cke command (/ cs, / ras, / cas, / we ) address a10 a11 udqm, ldqm dq0 to 15 pall ref ref ref act high ra ba high - z t rp t rca t rca t rca clk cke command (/ cs, / ras, / cas, / we ) address a10 a11 udqm, ldqm dq0 to 15 pall sref act ra ba high - z t rp t rca nop don't care nop self refresh ra ra t si t si 1clk
fedd56v161 61n - 0 1 msm56v161 61n 41 / 44 power down cycle notes : 1. rx = row address, bx = bank address = high or low level clk cke command (/ cs, / ras, / cas, / we ) address a10 a11 udqm, ldqm dq0 to 15 act act rb bb high - z active power down rb t si t si 1clk don't care nop pre nop t si don't care nop nop power down 1clk 1clk t si ra ba ra ba 1clk
fedd56v161 61n - 0 1 msm56v161 61n 42 / 44 package dimensions notes for mounting the surface mount type package the surface mount type packages are very susceptible to heat in reflow mounting and humidity absorbed in storage. therefore, before you perform reflow mounting, cont act a rohm sales office for the product name, package name, pin number, package code and desired mounting conditions (reflow method, temperature and times). (u nit : mm) notes: 1. lead with does not include trim offset. 2. package width and length do not include mold protrusion, diepad support protrusion and cavity offset between top and bo ttom cavity. 3. the seating plane is the surface which the package is mounted on and gets in contact with.
fedd56v161 61n - 0 1 msm56v161 61n 43 / 44 revision history document no. date page description previous edition current edition fedd 56v 16161n - 01 april 2 7 , 201 6 C C final edition 1
fedd56v161 61n - 0 1 msm56v161 61n 44 / 44 notes 1) the information contained herein is subject to change without notice. 2) although lapis semiconductor is continuously working to improve product reliability and quality, semiconductors can break dow n and malfunction due to various factors. therefore, in order to prevent personal injury or fire arising from failure, please take safety measures such as complying with the derating characteristics, implementing redundant and fire prevention designs, and utilizing backups and fail - safe procedures. lapis semiconductor shall have no responsibility for any damages arising out of the use of our products beyond the rating specified by lapis semiconductor. 3) examples of application circuits, circuit constants and any other information contained herein are provided only to illustrate the standard usage and operations of the products. the peripheral conditions must be taken into account when designing circuits for mass production. 4) the technical information specified herein is intended only to show the typical functions of the products and examples of application circuits for the products. no license, expressly or implied, is granted hereby under any intellectual property rights or other rights of lapis semiconductor or any third party with respect to the information contained in this document; therefore lapis semiconductor shall have no responsibility whatsoever for any dispute, concerning such rights owned by third parties, arising out of the use of such technical i nformation. 5) the products are intended for use in general electronic equipment (i.e. av/oa devices, communication, consumer systems, gaming/entertainment sets) as well as the applications indicated in this document. 6) the products specified in this document a re not designed to be radiation tolerant. 7) for use of our products in applications requiring a high degree of reliability (as exemplified below), please contact and consult with a lapis semiconductor representative: transportation equipment (i.e. cars, ship s, trains), primary communication equipment, traffic lights, fire/crime prevention, safety equipment, medical systems, servers, solar cells, and power transmission systems. 8) do not use our products in applications requiring extremely high reliability, such as aerospace equipment, nuclear power control systems, and submarine repeaters. 9) lapis semiconductor shall have no responsibility for any damages or injury arising from non - compliance with the recommended usage conditions and specifications contained herei n. 10) lapis semiconductor has used reasonable care to ensure the accuracy of the information contained in this document. however, lapis semiconductor does not warrant that such information is error - free and lapis semiconductor shall have no responsibility for any damages arising from any inaccuracy or misprint of such information. 11) please use the products in accordance with any applicable environmental laws and regulations, such as the rohs directive. for more details, including rohs compatibility, please conta ct a rohm sales office. lapis semiconductor shall have no responsibility for any damages or losses resulting non - compliance with any applicable laws or regulations. 12) when providing our products and technologies contained in this document to other countries, you must abide by the procedures and provisions stipulated in all applicable export laws and regulations, including without limitation the us export administration regulations and the foreign exchange and foreign trade act. 13) this document, in part or in wh ole, may not be reprinted or reproduced without prior consent of lapis semiconductor. copyright 20 16 lapis semiconductor co., ltd. 2 - 4 - 8 shinyokohama, kouhoku - ku, yokohama 222 - 8575, japan http://www.lapis - semi.com/en/

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